mirror of
https://github.com/openbsd/src.git
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Add smtiic(4), a driver for the I2C controller found on the SpacemiT K1
SoC. This is a close relative of mviic(4), but the register layout changed and some bits moved within the registers. ok jca@
This commit is contained in:
kettenis
@@ -1,4 +1,4 @@
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# $OpenBSD: GENERIC,v 1.59 2026/04/05 18:08:11 kettenis Exp $
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# $OpenBSD: GENERIC,v 1.60 2026/04/06 10:30:27 kettenis Exp $
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#
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# For further information on compiling OpenBSD kernels, see the config(8)
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# man page.
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@@ -76,6 +76,8 @@ sfuart* at fdt?
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smtclock* at fdt? early 1
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smtcomphy* at fdt?
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smtgpio* at fdt?
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smtiic* at fdt?
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iic* at smtiic?
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# StarFive SoCs
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stfclock* at fdt? early 1
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@@ -1,4 +1,4 @@
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# $OpenBSD: RAMDISK,v 1.51 2026/04/05 18:08:11 kettenis Exp $
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# $OpenBSD: RAMDISK,v 1.52 2026/04/06 10:30:27 kettenis Exp $
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machine riscv64
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maxusers 4
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@@ -67,6 +67,8 @@ sfuart* at fdt?
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smtclock* at fdt? early 1
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smtcomphy* at fdt?
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smtgpio* at fdt?
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smtiic* at fdt?
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iic* at smtiic?
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# StarFive SoCs
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stfclock* at fdt? early 1
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@@ -1,4 +1,4 @@
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# $OpenBSD: files.riscv64,v 1.34 2026/04/05 18:08:11 kettenis Exp $
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# $OpenBSD: files.riscv64,v 1.35 2026/04/06 10:30:27 kettenis Exp $
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# Standard stanzas config(8) can't run without
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maxpartitions 16
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@@ -140,6 +140,11 @@ device smtgpio
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attach smtgpio at fdt
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file arch/riscv64/dev/smtgpio.c smtgpio
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# SpacemiT I2C controller
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device smtiic: i2cbus
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attach smtiic at fdt
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file arch/riscv64/dev/smtiic.c smtiic
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# StarFive clock controller
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device stfclock
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attach stfclock at fdt
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@@ -1,4 +1,4 @@
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/* $OpenBSD: smtclock.c,v 1.1 2026/04/05 11:40:50 kettenis Exp $ */
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/* $OpenBSD: smtclock.c,v 1.2 2026/04/06 10:30:27 kettenis Exp $ */
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/*
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* Copyright (c) 2026 Mark Kettenis <kettenis@openbsd.org>
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*
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@@ -37,6 +37,22 @@
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#define K1_CLK_UART7 6
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#define K1_CLK_UART8 7
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#define K1_CLK_UART9 8
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#define K1_CLK_TWSI0 32
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#define K1_CLK_TWSI1 33
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#define K1_CLK_TWSI2 34
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#define K1_CLK_TWSI4 35
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#define K1_CLK_TWSI5 36
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#define K1_CLK_TWSI6 37
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#define K1_CLK_TWSI7 38
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#define K1_CLK_TWSI8 39
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#define K1_CLK_TWSI0_BUS 84
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#define K1_CLK_TWSI1_BUS 85
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#define K1_CLK_TWSI2_BUS 86
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#define K1_CLK_TWSI4_BUS 87
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#define K1_CLK_TWSI5_BUS 88
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#define K1_CLK_TWSI6_BUS 89
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#define K1_CLK_TWSI7_BUS 90
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#define K1_CLK_TWSI8_BUS 91
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/* APMU resets */
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#define K1_RESET_UART0 0
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@@ -48,6 +64,14 @@
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#define K1_RESET_UART7 6
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#define K1_RESET_UART8 7
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#define K1_RESET_UART9 8
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#define K1_RESET_TWSI0 32
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#define K1_RESET_TWSI1 33
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#define K1_RESET_TWSI2 34
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#define K1_RESET_TWSI4 35
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#define K1_RESET_TWSI5 36
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#define K1_RESET_TWSI6 37
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#define K1_RESET_TWSI7 38
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#define K1_RESET_TWSI8 39
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/* APMU clocks */
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#define K1_CLK_USB30 16
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@@ -63,11 +87,24 @@
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#define K1_RESET_PCIE0_SLAVE 24
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#define K1_RESET_PCIE0_DBI 25
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#define K1_RESET_PCIE0_GLOBAL 26
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#define K1_RESET_PCIE1_GLOBAL 30
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#define K1_RESET_PCIE2_GLOBAL 34
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/* APBC registers */
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#define APBC_UART1_CLK_RST 0x0000
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#define APBC_UART2_CLK_RST 0x0004
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#define APBC_TWSI8_CLK_RST 0x0020
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#define APBC_TWSI8_CLK_RST_RST (1U << 2)
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#define APBC_TWSI8_CLK_RST_FNCLK (1U << 1)
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#define APBC_TWSI8_CLK_RST_APBCLK (1U << 0)
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#define APBC_UART3_CLK_RST 0x0024
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#define APBC_TWSI0_CLK_RST 0x002c
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#define APBC_TWSI1_CLK_RST 0x0030
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#define APBC_TWSI2_CLK_RST 0x0038
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#define APBC_TWSI4_CLK_RST 0x0040
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#define APBC_TWSI5_CLK_RST 0x004c
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#define APBC_TWSI6_CLK_RST 0x0060
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#define APBC_TWSI7_CLK_RST 0x0068
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#define APBC_UART4_CLK_RST 0x0070
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#define APBC_UART5_CLK_RST 0x0074
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#define APBC_UART6_CLK_RST 0x0078
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@@ -79,6 +116,8 @@
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/* APMU registers */
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#define APMU_USB_CLK_RES_CTRL 0x005c
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#define APMU_PCIE_CLK_RES_CTRL_PORTA 0x03cc
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#define APMU_PCIE_CLK_RES_CTRL_PORTB 0x03d4
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#define APMU_PCIE_CLK_RES_CTRL_PORTC 0x03dc
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#define HREAD4(sc, reg) \
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(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
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@@ -112,6 +151,22 @@ static struct smtclock k1_apbc_clocks[] = {
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{ K1_CLK_UART7, APBC_UART7_CLK_RST, 1 },
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{ K1_CLK_UART8, APBC_UART8_CLK_RST, 1 },
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{ K1_CLK_UART9, APBC_UART9_CLK_RST, 1 },
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{ K1_CLK_TWSI0, APBC_TWSI0_CLK_RST, 1 },
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{ K1_CLK_TWSI1, APBC_TWSI1_CLK_RST, 1 },
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{ K1_CLK_TWSI2, APBC_TWSI2_CLK_RST, 1 },
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{ K1_CLK_TWSI4, APBC_TWSI4_CLK_RST, 1 },
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{ K1_CLK_TWSI5, APBC_TWSI5_CLK_RST, 1 },
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{ K1_CLK_TWSI6, APBC_TWSI6_CLK_RST, 1 },
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{ K1_CLK_TWSI7, APBC_TWSI7_CLK_RST, 1 },
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{ K1_CLK_TWSI8, APBC_TWSI8_CLK_RST, 1 },
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{ K1_CLK_TWSI0_BUS, APBC_TWSI0_CLK_RST, 0 },
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{ K1_CLK_TWSI1_BUS, APBC_TWSI1_CLK_RST, 0 },
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{ K1_CLK_TWSI2_BUS, APBC_TWSI2_CLK_RST, 0 },
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{ K1_CLK_TWSI4_BUS, APBC_TWSI4_CLK_RST, 0 },
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{ K1_CLK_TWSI5_BUS, APBC_TWSI5_CLK_RST, 0 },
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{ K1_CLK_TWSI6_BUS, APBC_TWSI6_CLK_RST, 0 },
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{ K1_CLK_TWSI7_BUS, APBC_TWSI7_CLK_RST, 0 },
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{ K1_CLK_TWSI8_BUS, APBC_TWSI8_CLK_RST, 0 },
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{ -1 },
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};
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@@ -125,6 +180,14 @@ static struct smtreset k1_apbc_resets[] = {
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{ K1_RESET_UART7, APBC_UART1_CLK_RST, 2, -1 },
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{ K1_RESET_UART8, APBC_UART1_CLK_RST, 2, -1 },
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{ K1_RESET_UART9, APBC_UART1_CLK_RST, 2, -1 },
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{ K1_RESET_TWSI0, APBC_TWSI0_CLK_RST, 2, -1 },
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{ K1_RESET_TWSI1, APBC_TWSI1_CLK_RST, 2, -1 },
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{ K1_RESET_TWSI2, APBC_TWSI2_CLK_RST, 2, -1 },
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{ K1_RESET_TWSI4, APBC_TWSI4_CLK_RST, 2, -1 },
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{ K1_RESET_TWSI5, APBC_TWSI5_CLK_RST, 2, -1 },
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{ K1_RESET_TWSI6, APBC_TWSI6_CLK_RST, 2, -1 },
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{ K1_RESET_TWSI7, APBC_TWSI7_CLK_RST, 2, -1 },
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{ K1_RESET_TWSI8, APBC_TWSI8_CLK_RST, 2, -1 },
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{ -1 },
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};
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@@ -144,6 +207,8 @@ static struct smtreset k1_apmu_resets[] = {
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{ K1_RESET_PCIE0_SLAVE, APMU_PCIE_CLK_RES_CTRL_PORTA, -1, 4 },
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{ K1_RESET_PCIE0_DBI, APMU_PCIE_CLK_RES_CTRL_PORTA, -1, 3 },
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{ K1_RESET_PCIE0_GLOBAL, APMU_PCIE_CLK_RES_CTRL_PORTA, 8, -1 },
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{ K1_RESET_PCIE1_GLOBAL, APMU_PCIE_CLK_RES_CTRL_PORTB, 8, -1 },
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{ K1_RESET_PCIE2_GLOBAL, APMU_PCIE_CLK_RES_CTRL_PORTC, 8, -1 },
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{ -1 },
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};
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@@ -301,6 +366,25 @@ smtclock_enable(void *cookie, uint32_t *cells, int on)
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return;
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}
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if (OF_is_compatible(sc->sc_node, "spacemit,k1-syscon-apbc")) {
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/*
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* To work around the fact that the APBC_TWSI8_CLK_RST
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* register is write-only, we enable both clocks and
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* clear the reset at the same time.
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*/
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switch (idx) {
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case K1_CLK_TWSI8:
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case K1_CLK_TWSI8_BUS:
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if (on)
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HWRITE4(sc, APBC_TWSI8_CLK_RST,
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APBC_TWSI8_CLK_RST_FNCLK |
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APBC_TWSI8_CLK_RST_APBCLK);
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else
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HWRITE4(sc, clock->reg, 0);
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return;
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}
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}
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if (on)
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HSET4(sc, clock->reg, (1U << clock->bit));
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else
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@@ -327,6 +411,25 @@ smtclock_reset(void *cookie, uint32_t *cells, int assert)
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return;
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}
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if (OF_is_compatible(sc->sc_node, "spacemit,k1-syscon-apbc")) {
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/*
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* To work around the fact that the APBC_TWSI8_CLK_RST
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* register is write-only, we enable both clocks and
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* clear the reset at the same time.
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*/
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switch (idx) {
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case K1_RESET_TWSI8:
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if (assert)
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HWRITE4(sc, APBC_TWSI8_CLK_RST,
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APBC_TWSI8_CLK_RST_RST);
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else
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HWRITE4(sc, APBC_TWSI8_CLK_RST,
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APBC_TWSI8_CLK_RST_FNCLK |
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APBC_TWSI8_CLK_RST_APBCLK);
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return;
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}
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}
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if (reset->assert_bit != -1)
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assert_mask = (1U << reset->assert_bit);
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if (reset->deassert_bit != -1)
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324
sys/arch/riscv64/dev/smtiic.c
Normal file
324
sys/arch/riscv64/dev/smtiic.c
Normal file
@@ -0,0 +1,324 @@
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/* $OpenBSD: smtiic.c,v 1.1 2026/04/06 10:30:27 kettenis Exp $ */
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/*
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* Copyright (c) 2019 Patrick Wildt <patrick@blueri.se>
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* Copyright (c) 2026 Mark Kettenis <kettenis@openbsd.org>
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <sys/param.h>
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#include <sys/device.h>
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#include <sys/kernel.h>
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#include <sys/systm.h>
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#define _I2C_PRIVATE
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#include <dev/i2c/i2cvar.h>
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#include <machine/bus.h>
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#include <machine/fdt.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_clock.h>
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#include <dev/ofw/ofw_pinctrl.h>
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#include <dev/ofw/ofw_misc.h>
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#include <dev/ofw/fdt.h>
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/* registers */
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#define ICR 0x00
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#define ICR_BEIE (1U << 22)
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#define ICR_GCD (1U << 21)
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#define ICR_DRFIE (1U << 20)
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#define ICR_ITEIE (1U << 19)
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#define ICR_IUE (1U << 14)
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#define ICR_SCLE (1U << 13)
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#define ICR_UR (1U << 10)
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#define ICR_MODE_MASK (0x3 << 8)
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#define ICR_MODE_FAST (0x1 << 8)
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#define ICR_TB (1U << 3)
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#define ICR_ACKNAK (1U << 2)
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#define ICR_STOP (1U << 1)
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#define ICR_START (1U << 0)
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#define ISR 0x04
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#define ISR_INIT 0xfdfc0000
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#define ISR_BED (1U << 22)
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#define ISR_IRF (1U << 20)
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#define ISR_ITE (1U << 19)
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#define ISR_IBB (1U << 16)
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#define ISR_UB (1U << 15)
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#define ISR_ACKNAK (1U << 14)
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#define IDBR 0x0c
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struct smtiic_softc {
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struct device sc_dev;
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_ioh;
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int sc_node;
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uint32_t sc_freq;
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struct i2c_controller sc_ic;
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};
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int smtiic_match(struct device *, void *, void *);
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void smtiic_attach(struct device *, struct device *, void *);
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#define HREAD4(sc, reg) \
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(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
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#define HWRITE4(sc, reg, val) \
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bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
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#define HSET4(sc, reg, bits) \
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HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
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#define HCLR4(sc, reg, bits) \
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HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
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const struct cfattach smtiic_ca = {
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sizeof(struct smtiic_softc), smtiic_match, smtiic_attach
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};
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struct cfdriver smtiic_cd = {
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NULL, "smtiic", DV_DULL
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};
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int smtiic_i2c_acquire_bus(void *, int);
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void smtiic_i2c_release_bus(void *, int);
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int smtiic_wait_state(struct smtiic_softc *, uint32_t, uint32_t);
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int smtiic_send_start(void *, int);
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int smtiic_send_stop(void *, int);
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int smtiic_initiate_xfer(void *, i2c_addr_t, int);
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int smtiic_read_byte(void *, uint8_t *, int);
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int smtiic_write_byte(void *, uint8_t, int);
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void smtiic_bus_scan(struct device *, struct i2cbus_attach_args *, void *);
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int
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smtiic_match(struct device *parent, void *match, void *aux)
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{
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struct fdt_attach_args *faa = aux;
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return OF_is_compatible(faa->fa_node, "spacemit,k1-i2c");
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}
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void
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smtiic_attach(struct device *parent, struct device *self, void *aux)
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{
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struct smtiic_softc *sc = (struct smtiic_softc *)self;
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struct fdt_attach_args *faa = aux;
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struct i2cbus_attach_args iba;
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if (faa->fa_nreg < 1) {
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printf(": no registers\n");
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return;
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}
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sc->sc_iot = faa->fa_iot;
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if (bus_space_map(sc->sc_iot, faa->fa_reg[0].addr,
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faa->fa_reg[0].size, 0, &sc->sc_ioh)) {
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printf(": can't map registers\n");
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return;
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}
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sc->sc_node = faa->fa_node;
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printf("\n");
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pinctrl_byname(sc->sc_node, "default");
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clock_enable_all(sc->sc_node);
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reset_deassert_all(sc->sc_node);
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sc->sc_freq = OF_getpropint(sc->sc_node, "clock-frequency", 100000);
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/* reset */
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HWRITE4(sc, ICR, ICR_UR);
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delay(5);
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HWRITE4(sc, ICR, 0);
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HWRITE4(sc, ISR, ISR_INIT);
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/* set defaults */
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HSET4(sc, ICR, ICR_SCLE | ICR_GCD);
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if (sc->sc_freq == 400000)
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HSET4(sc, ICR, ICR_MODE_FAST);
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sc->sc_ic.ic_cookie = sc;
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sc->sc_ic.ic_acquire_bus = smtiic_i2c_acquire_bus;
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sc->sc_ic.ic_release_bus = smtiic_i2c_release_bus;
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sc->sc_ic.ic_exec = NULL;
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sc->sc_ic.ic_send_start = smtiic_send_start;
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||||
sc->sc_ic.ic_send_stop = smtiic_send_stop;
|
||||
sc->sc_ic.ic_initiate_xfer = smtiic_initiate_xfer;
|
||||
sc->sc_ic.ic_read_byte = smtiic_read_byte;
|
||||
sc->sc_ic.ic_write_byte = smtiic_write_byte;
|
||||
|
||||
bzero(&iba, sizeof iba);
|
||||
iba.iba_name = "iic";
|
||||
iba.iba_tag = &sc->sc_ic;
|
||||
iba.iba_bus_scan = smtiic_bus_scan;
|
||||
iba.iba_bus_scan_arg = &sc->sc_node;
|
||||
config_found(&sc->sc_dev, &iba, iicbus_print);
|
||||
}
|
||||
|
||||
int
|
||||
smtiic_wait_state(struct smtiic_softc *sc, uint32_t mask, uint32_t value)
|
||||
{
|
||||
uint32_t state;
|
||||
int timeout;
|
||||
|
||||
for (timeout = 1000; timeout > 0; timeout--) {
|
||||
if (((state = HREAD4(sc, ISR)) & mask) == value)
|
||||
return 0;
|
||||
delay(10);
|
||||
}
|
||||
return ETIMEDOUT;
|
||||
}
|
||||
|
||||
int
|
||||
smtiic_i2c_acquire_bus(void *cookie, int flags)
|
||||
{
|
||||
struct smtiic_softc *sc = cookie;
|
||||
|
||||
HSET4(sc, ICR, ICR_IUE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void
|
||||
smtiic_i2c_release_bus(void *cookie, int flags)
|
||||
{
|
||||
struct smtiic_softc *sc = cookie;
|
||||
|
||||
HCLR4(sc, ICR, ICR_IUE);
|
||||
}
|
||||
|
||||
int
|
||||
smtiic_send_start(void *v, int flags)
|
||||
{
|
||||
struct smtiic_softc *sc = v;
|
||||
|
||||
HSET4(sc, ICR, ICR_START);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
smtiic_send_stop(void *v, int flags)
|
||||
{
|
||||
struct smtiic_softc *sc = v;
|
||||
|
||||
HSET4(sc, ICR, ICR_STOP);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
smtiic_initiate_xfer(void *v, i2c_addr_t addr, int flags)
|
||||
{
|
||||
struct smtiic_softc *sc = v;
|
||||
|
||||
if (smtiic_wait_state(sc, ISR_IBB, 0))
|
||||
return EIO;
|
||||
|
||||
HCLR4(sc, ICR, ICR_START);
|
||||
HCLR4(sc, ICR, ICR_STOP);
|
||||
HCLR4(sc, ICR, ICR_ACKNAK);
|
||||
if (flags & I2C_F_READ)
|
||||
HWRITE4(sc, IDBR, addr << 1 | 1);
|
||||
else
|
||||
HWRITE4(sc, IDBR, addr << 1);
|
||||
HSET4(sc, ICR, ICR_START);
|
||||
|
||||
HSET4(sc, ICR, ICR_TB);
|
||||
if (smtiic_wait_state(sc, ISR_ITE, ISR_ITE))
|
||||
return EIO;
|
||||
HWRITE4(sc, ISR, ISR_ITE);
|
||||
if (HREAD4(sc, ISR) & ISR_ACKNAK)
|
||||
return EIO;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
smtiic_read_byte(void *v, uint8_t *valp, int flags)
|
||||
{
|
||||
struct smtiic_softc *sc = v;
|
||||
|
||||
if (smtiic_wait_state(sc, ISR_IBB, 0))
|
||||
return EIO;
|
||||
|
||||
HCLR4(sc, ICR, ICR_START);
|
||||
HCLR4(sc, ICR, ICR_STOP);
|
||||
HCLR4(sc, ICR, ICR_ACKNAK);
|
||||
if ((flags & (I2C_F_LAST | I2C_F_STOP)) == (I2C_F_LAST | I2C_F_STOP))
|
||||
HSET4(sc, ICR, ICR_STOP);
|
||||
if (flags & I2C_F_LAST)
|
||||
HSET4(sc, ICR, ICR_ACKNAK);
|
||||
|
||||
HSET4(sc, ICR, ICR_TB);
|
||||
if (smtiic_wait_state(sc, ISR_IRF, ISR_IRF))
|
||||
return EIO;
|
||||
*valp = HREAD4(sc, IDBR);
|
||||
HWRITE4(sc, ISR, ISR_IRF);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
smtiic_write_byte(void *v, uint8_t val, int flags)
|
||||
{
|
||||
struct smtiic_softc *sc = v;
|
||||
|
||||
HCLR4(sc, ICR, ICR_START);
|
||||
HCLR4(sc, ICR, ICR_STOP);
|
||||
HCLR4(sc, ICR, ICR_ACKNAK);
|
||||
HWRITE4(sc, IDBR, val);
|
||||
if (flags & I2C_F_STOP)
|
||||
HSET4(sc, ICR, ICR_STOP);
|
||||
|
||||
HSET4(sc, ICR, ICR_TB);
|
||||
if (smtiic_wait_state(sc, ISR_ITE, ISR_ITE))
|
||||
return EIO;
|
||||
HWRITE4(sc, ISR, ISR_ITE);
|
||||
if (HREAD4(sc, ISR) & ISR_ACKNAK)
|
||||
return EIO;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void
|
||||
smtiic_bus_scan(struct device *self, struct i2cbus_attach_args *iba, void *aux)
|
||||
{
|
||||
int iba_node = *(int *)aux;
|
||||
struct i2c_attach_args ia;
|
||||
char name[32];
|
||||
uint32_t reg[1];
|
||||
int node;
|
||||
|
||||
for (node = OF_child(iba_node); node; node = OF_peer(node)) {
|
||||
memset(name, 0, sizeof(name));
|
||||
memset(reg, 0, sizeof(reg));
|
||||
|
||||
if (!OF_is_enabled(node))
|
||||
continue;
|
||||
|
||||
if (OF_getprop(node, "compatible", name, sizeof(name)) == -1)
|
||||
continue;
|
||||
if (name[0] == '\0')
|
||||
continue;
|
||||
|
||||
if (OF_getprop(node, "reg", ®, sizeof(reg)) != sizeof(reg))
|
||||
continue;
|
||||
|
||||
memset(&ia, 0, sizeof(ia));
|
||||
ia.ia_tag = iba->iba_tag;
|
||||
ia.ia_addr = bemtoh32(®[0]);
|
||||
ia.ia_name = name;
|
||||
ia.ia_cookie = &node;
|
||||
config_found(self, &ia, iic_print);
|
||||
}
|
||||
}
|
||||
Reference in New Issue
Block a user