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Add a few more PCIe related clocks and resets.

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ok mlarkin@, deraadt@
This commit is contained in:
kettenis
2026-04-07 08:28:34 +00:00
parent d8bd1b9877
commit 6216598462
1 changed files with 25 additions and 1 deletions
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26
sys/arch/riscv64/dev/smtclock.c
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@@ -1,4 +1,4 @@
/* $OpenBSD: smtclock.c,v 1.2 2026/04/06 10:30:27 kettenis Exp $ */
/* $OpenBSD: smtclock.c,v 1.3 2026/04/07 08:28:34 kettenis Exp $ */
/*
* Copyright (c) 2026 Mark Kettenis <kettenis@openbsd.org>
*
@@ -78,6 +78,12 @@
#define K1_CLK_PCIE0_MASTER 28
#define K1_CLK_PCIE0_SLAVE 29
#define K1_CLK_PCIE0_DBI 30
#define K1_CLK_PCIE1_MASTER 31
#define K1_CLK_PCIE1_SLAVE 32
#define K1_CLK_PCIE1_DBI 33
#define K1_CLK_PCIE2_MASTER 34
#define K1_CLK_PCIE2_SLAVE 35
#define K1_CLK_PCIE2_DBI 36
/* APMU resets */
#define K1_RESET_USB30_AHB 8
@@ -87,7 +93,13 @@
#define K1_RESET_PCIE0_SLAVE 24
#define K1_RESET_PCIE0_DBI 25
#define K1_RESET_PCIE0_GLOBAL 26
#define K1_RESET_PCIE1_MASTER 27
#define K1_RESET_PCIE1_SLAVE 28
#define K1_RESET_PCIE1_DBI 29
#define K1_RESET_PCIE1_GLOBAL 30
#define K1_RESET_PCIE2_MASTER 31
#define K1_RESET_PCIE2_SLAVE 32
#define K1_RESET_PCIE2_DBI 33
#define K1_RESET_PCIE2_GLOBAL 34
/* APBC registers */
@@ -196,6 +208,12 @@ static struct smtclock k1_apmu_clocks[] = {
{ K1_CLK_PCIE0_MASTER, APMU_PCIE_CLK_RES_CTRL_PORTA, 2 },
{ K1_CLK_PCIE0_SLAVE, APMU_PCIE_CLK_RES_CTRL_PORTA, 1 },
{ K1_CLK_PCIE0_DBI, APMU_PCIE_CLK_RES_CTRL_PORTA, 0 },
{ K1_CLK_PCIE1_MASTER, APMU_PCIE_CLK_RES_CTRL_PORTB, 2 },
{ K1_CLK_PCIE1_SLAVE, APMU_PCIE_CLK_RES_CTRL_PORTB, 1 },
{ K1_CLK_PCIE1_DBI, APMU_PCIE_CLK_RES_CTRL_PORTB, 0 },
{ K1_CLK_PCIE2_MASTER, APMU_PCIE_CLK_RES_CTRL_PORTC, 2 },
{ K1_CLK_PCIE2_SLAVE, APMU_PCIE_CLK_RES_CTRL_PORTC, 1 },
{ K1_CLK_PCIE2_DBI, APMU_PCIE_CLK_RES_CTRL_PORTC, 0 },
{ -1 },
};
@@ -207,7 +225,13 @@ static struct smtreset k1_apmu_resets[] = {
{ K1_RESET_PCIE0_SLAVE, APMU_PCIE_CLK_RES_CTRL_PORTA, -1, 4 },
{ K1_RESET_PCIE0_DBI, APMU_PCIE_CLK_RES_CTRL_PORTA, -1, 3 },
{ K1_RESET_PCIE0_GLOBAL, APMU_PCIE_CLK_RES_CTRL_PORTA, 8, -1 },
{ K1_RESET_PCIE1_MASTER, APMU_PCIE_CLK_RES_CTRL_PORTB, -1, 5 },
{ K1_RESET_PCIE1_SLAVE, APMU_PCIE_CLK_RES_CTRL_PORTB, -1, 4 },
{ K1_RESET_PCIE1_DBI, APMU_PCIE_CLK_RES_CTRL_PORTB, -1, 3 },
{ K1_RESET_PCIE1_GLOBAL, APMU_PCIE_CLK_RES_CTRL_PORTB, 8, -1 },
{ K1_RESET_PCIE2_MASTER, APMU_PCIE_CLK_RES_CTRL_PORTC, -1, 5 },
{ K1_RESET_PCIE2_SLAVE, APMU_PCIE_CLK_RES_CTRL_PORTC, -1, 4 },
{ K1_RESET_PCIE2_DBI, APMU_PCIE_CLK_RES_CTRL_PORTC, -1, 3 },
{ K1_RESET_PCIE2_GLOBAL, APMU_PCIE_CLK_RES_CTRL_PORTC, 8, -1 },
{ -1 },
};