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Add SpacemiT K1 support.
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kettenis
@@ -1,4 +1,4 @@
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/* $OpenBSD: dwpcie.c,v 1.58 2026/01/25 12:09:50 kettenis Exp $ */
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/* $OpenBSD: dwpcie.c,v 1.59 2026/04/07 20:38:51 kettenis Exp $ */
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/*
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* Copyright (c) 2018 Mark Kettenis <kettenis@openbsd.org>
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*
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@@ -322,7 +322,8 @@ dwpcie_match(struct device *parent, void *match, void *aux)
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OF_is_compatible(faa->fa_node, "qcom,pcie-x1e80100") ||
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OF_is_compatible(faa->fa_node, "rockchip,rk3568-pcie") ||
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OF_is_compatible(faa->fa_node, "rockchip,rk3588-pcie") ||
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OF_is_compatible(faa->fa_node, "sifive,fu740-pcie"));
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OF_is_compatible(faa->fa_node, "sifive,fu740-pcie") ||
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OF_is_compatible(faa->fa_node, "spacemit,k1-pcie"));
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}
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void dwpcie_attach_deferred(struct device *);
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@@ -345,6 +346,8 @@ int dwpcie_imx8mq_intr(void *);
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int dwpcie_fu740_init(struct dwpcie_softc *);
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int dwpcie_k1_init(struct dwpcie_softc *);
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int dwpcie_rk3568_init(struct dwpcie_softc *);
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int dwpcie_rk3568_intr(void *);
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void *dwpcie_rk3568_intr_establish(void *, int *, int,
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@@ -443,6 +446,17 @@ dwpcie_attach(struct device *parent, struct device *self, void *aux)
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sc->sc_glue_size = faa->fa_reg[glue].size;
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}
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if (OF_is_compatible(faa->fa_node, "spacemit,k1-pcie")) {
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glue = OF_getindex(faa->fa_node, "link", "reg-names");
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if (glue < 0 || glue >= faa->fa_nreg) {
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printf(": no link registers\n");
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return;
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}
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sc->sc_glue_base = faa->fa_reg[glue].addr;
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sc->sc_glue_size = faa->fa_reg[glue].size;
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}
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sc->sc_iot = faa->fa_iot;
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sc->sc_dmat = faa->fa_dmat;
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sc->sc_node = faa->fa_node;
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@@ -548,6 +562,8 @@ dwpcie_attach_deferred(struct device *self)
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error = dwpcie_rk3568_init(sc);
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if (OF_is_compatible(sc->sc_node, "sifive,fu740-pcie"))
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error = dwpcie_fu740_init(sc);
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if (OF_is_compatible(sc->sc_node, "spacemit,k1-pcie"))
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error = dwpcie_k1_init(sc);
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if (error != 0) {
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bus_space_unmap(sc->sc_iot, sc->sc_conf_ioh, sc->sc_conf_size);
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bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ctrl_size);
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@@ -754,6 +770,29 @@ dwpcie_attach_deferred(struct device *self)
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config_found(self, &pba, NULL);
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}
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int
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dwpcie_get_capability(struct dwpcie_softc *sc, int capid, int *offset,
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pcireg_t *value)
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{
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pcireg_t reg;
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unsigned int ofs;
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ofs = PCI_CAPLIST_PTR(HREAD4(sc, PCI_CAPLISTPTR_REG));
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while (ofs != 0) {
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reg = HREAD4(sc, ofs);
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if (PCI_CAPLIST_CAP(reg) == capid) {
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if (offset)
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*offset = ofs;
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if (value)
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*value = reg;
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return 1;
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}
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ofs = PCI_CAPLIST_NEXT(reg);
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}
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return 0;
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}
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void
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dwpcie_link_config(struct dwpcie_softc *sc)
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{
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@@ -1337,6 +1376,123 @@ dwpcie_fu740_init(struct dwpcie_softc *sc)
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return 0;
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}
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/* SpacemiT K1 registers */
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#define APMU_PCIE_CLK_RES_CTRL 0x0000
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#define APMU_PCIE_DEVICE_TYPE_SEL (1U << 31)
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#define APMU_PCIE_APP_HOLD_PHY_RST (1U << 30)
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#define APMU_PCIE_RC_PERST (1U << 12)
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#define APMU_PCIE_SYS_AUX_PWR_DET (1U << 9)
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#define APMU_PCIE_LTSSM_EN (1U << 6)
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#define APMU_PCIE_CTRL_LOGIC 0x0004
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#define APMU_PCIE_SOFT_RESET (1U << 0)
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#define K1_PHY_AHB_IRQ 0x0000
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#define K1_PHY_AHB_IRQ_EN (1U << 0)
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#define K1_PHY_AHB_IRQENABLE_MSI 0x0014
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#define K1_PHY_AHB_IRQENABLE_MSI_EN (1U << 11)
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int
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dwpcie_k1_init(struct dwpcie_softc *sc)
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{
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struct regmap *apmu_rm;
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uint32_t apmu[2], val;
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int error, off, timo;
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sc->sc_num_viewport = 8;
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if (bus_space_map(sc->sc_iot, sc->sc_glue_base,
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sc->sc_glue_size, 0, &sc->sc_glue_ioh))
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return ENOMEM;
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if (OF_getpropintarray(sc->sc_node, "spacemit,apmu",
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apmu, sizeof(apmu)) != sizeof(apmu))
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return EINVAL;
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apmu_rm = regmap_byphandle(apmu[0]);
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if (apmu_rm == NULL)
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return ENXIO;
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/* Hold PHY in reset until starting the link. */
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val = regmap_read_4(apmu_rm, apmu[1] + APMU_PCIE_CLK_RES_CTRL);
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val |= APMU_PCIE_APP_HOLD_PHY_RST;
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val &= ~APMU_PCIE_LTSSM_EN;
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regmap_write_4(apmu_rm, apmu[1] + APMU_PCIE_CLK_RES_CTRL, val);
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/* Soft reset. */
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val = regmap_read_4(apmu_rm, apmu[1] + APMU_PCIE_CTRL_LOGIC);
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regmap_write_4(apmu_rm, apmu[1] + APMU_PCIE_CTRL_LOGIC,
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val | APMU_PCIE_SOFT_RESET);
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regmap_read_4(apmu_rm, apmu[1] + APMU_PCIE_CTRL_LOGIC);
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delay(2000);
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regmap_write_4(apmu_rm, apmu[1] + APMU_PCIE_CTRL_LOGIC,
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val &= ~APMU_PCIE_SOFT_RESET);
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clock_enable_all(sc->sc_node);
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reset_deassert_all(sc->sc_node);
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/* Set vendor ID and product ID. (*/
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HSET4(sc, MISC_CONTROL_1, MISC_CONTROL_1_DBI_RO_WR_EN);
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HWRITE4(sc, PCI_ID_REG,
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PCI_VENDOR_SPACEMIT << PCI_VENDOR_SHIFT |
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PCI_PRODUCT_SPACEMIT_K1 << PCI_PRODUCT_SHIFT);
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HCLR4(sc, MISC_CONTROL_1, MISC_CONTROL_1_DBI_RO_WR_EN);
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/* Assert PERST#. */
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val = regmap_read_4(apmu_rm, apmu[1] + APMU_PCIE_CLK_RES_CTRL);
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regmap_write_4(apmu_rm, apmu[1] + APMU_PCIE_CLK_RES_CTRL,
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val | APMU_PCIE_RC_PERST);
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regmap_read_4(apmu_rm, apmu[1] + APMU_PCIE_CLK_RES_CTRL);
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delay(100000);
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/* Set RC mode; indicate Vaux presence. */
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val = regmap_read_4(apmu_rm, apmu[1] + APMU_PCIE_CLK_RES_CTRL);
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regmap_write_4(apmu_rm, apmu[1] + APMU_PCIE_CLK_RES_CTRL,
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val | APMU_PCIE_DEVICE_TYPE_SEL | APMU_PCIE_SYS_AUX_PWR_DET);
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phy_enable_idx(OF_child(sc->sc_node), 0);
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/* Deassert PERST#. */
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val = regmap_read_4(apmu_rm, apmu[1] + APMU_PCIE_CLK_RES_CTRL);
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regmap_write_4(apmu_rm, apmu[1] + APMU_PCIE_CLK_RES_CTRL,
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val & ~APMU_PCIE_RC_PERST);
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/* Disable ASPM L1. */
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if (!dwpcie_get_capability(sc, PCI_CAP_PCIEXPRESS, &off, NULL))
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return ENXIO;
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HSET4(sc, MISC_CONTROL_1, MISC_CONTROL_1_DBI_RO_WR_EN);
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val = HREAD4(sc, off + PCI_PCIE_LCAP);
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val &= ~PCI_PCIE_LCAP_ASPM_L1;
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HWRITE4(sc, off + PCI_PCIE_LCAP, val);
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HCLR4(sc, MISC_CONTROL_1, MISC_CONTROL_1_DBI_RO_WR_EN);
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error = dwpcie_msi_init(sc);
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if (error)
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return error;
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val = regmap_read_4(apmu_rm, apmu[1] + APMU_PCIE_CLK_RES_CTRL);
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val &= ~APMU_PCIE_APP_HOLD_PHY_RST;
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val |= APMU_PCIE_LTSSM_EN;
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regmap_write_4(apmu_rm, apmu[1] + APMU_PCIE_CLK_RES_CTRL, val);
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/* Enable MSIs */
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bus_space_write_4(sc->sc_iot, sc->sc_glue_ioh,
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K1_PHY_AHB_IRQENABLE_MSI, K1_PHY_AHB_IRQENABLE_MSI_EN);
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val = bus_space_read_4(sc->sc_iot, sc->sc_glue_ioh, K1_PHY_AHB_IRQ);
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bus_space_write_4(sc->sc_iot, sc->sc_glue_ioh, K1_PHY_AHB_IRQ,
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val | K1_PHY_AHB_IRQ_EN);
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/* Wait for the link to come up. */
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for (timo = 20000; timo > 0; timo--) {
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if (dwpcie_link_up(sc))
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break;
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delay(10);
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}
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if (timo == 0)
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return ETIMEDOUT;
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return 0;
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}
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int
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dwpcie_rk3568_link_up(struct dwpcie_softc *sc)
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{
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