From da96c44cc29850cbd5397dffce63d7e23931050e Mon Sep 17 00:00:00 2001 From: jsg Date: Wed, 25 Mar 2026 23:12:30 +0000 Subject: [PATCH] drm/i915/psr: Write DSC parameters on Selective Update in ET mode From Jouni Hogander 4ab7c9fa0a477ebe4eb40847f85bfbcb70dfd653 in linux-6.18.y/6.18.20 5923a6e0459fdd3edac4ad5abccb24d777d8f1b6 in mainline linux --- sys/dev/pci/drm/i915/display/intel_psr.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/sys/dev/pci/drm/i915/display/intel_psr.c b/sys/dev/pci/drm/i915/display/intel_psr.c index a4e2c7f6615..1140b439250 100644 --- a/sys/dev/pci/drm/i915/display/intel_psr.c +++ b/sys/dev/pci/drm/i915/display/intel_psr.c @@ -50,6 +50,7 @@ #include "intel_snps_phy.h" #include "intel_step.h" #include "intel_vblank.h" +#include "intel_vdsc.h" #include "intel_vrr.h" #include "skl_universal_plane.h" @@ -2489,6 +2490,12 @@ void intel_psr2_program_trans_man_trk_ctl(struct intel_dsb *dsb, intel_de_write_dsb(display, dsb, PIPE_SRCSZ_ERLY_TPT(crtc->pipe), crtc_state->pipe_srcsz_early_tpt); + + if (!crtc_state->dsc.compression_enable) + return; + + intel_dsc_su_et_parameters_configure(dsb, encoder, crtc_state, + drm_rect_height(&crtc_state->psr2_su_area)); } static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state, @@ -2909,6 +2916,10 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, } skip_sel_fetch_set_loop: + if (full_update) + clip_area_update(&crtc_state->psr2_su_area, &crtc_state->pipe_src, + &crtc_state->pipe_src); + psr2_man_trk_ctl_calc(crtc_state, full_update); crtc_state->pipe_srcsz_early_tpt = psr2_pipe_srcsz_early_tpt_calc(crtc_state, full_update);